Tags · Tim Oliver / tt · GitLab

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release-4-12-12

2576eea5 · Corrected Genkins timing problem. · Sep 14, 2017

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release-4-12-11

90025998 · Corrected Micogen issue 0069 : bug in ffts. · Sep 12, 2017

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release-4-12-10

4e5602c2 · vsip_finalize issue resolved. · Sep 08, 2017

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release-4-12-9

d19b2e4d · Added Intel VxWorks mods from CW work. · Sep 01, 2017

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release-4-12-8

0e31b450 · Corrected Micogeng Issue 0068 (cvexp) · Aug 28, 2017

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release-4-12-7

9f4e3f20 · Corrected bug 0068: vsip_cexp_f - system sin/cosine not performing full range... · Aug 17, 2017

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release-4-12-6

258be42e · Added Phi mods: phi make test now works for vsipl full and dfull · Jul 12, 2017

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release-4-12-5

8c12081b · Added quick time option to C backend. · Jul 03, 2017

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release-4-12-4

fdffe590 · corrected CSIPL and Radstone for conflicts with last checkin · Jun 30, 2017

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release-4-12-3

888969f0 · Sped up timing suite. Corrected timing functions for cchold and chold. · Jun 29, 2017

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release-4-12-2

9d6e7954 · updated manuals for Curtiss-Wright · Jun 23, 2017

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release-4-12-1

209240f0 · version 4.12.1 checked in · Jun 23, 2017

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release-4-12-0

56d70c6b · T2080 mods for Kelly prepared for 16/6/17 release · Jun 21, 2017

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release-4-11-1

744d66bf · version 4.11.1: added hr2 changes · Apr 19, 2017

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release-4-11-0

25fb40e2 · Added licence manager. LICENCED=yes · Apr 10, 2017

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release-4-10-4

bc70fc10 · corrected bug in real fftw library on ARCH=intel32 BACKEND=intel FRONTEND=fftw · Apr 07, 2017

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release-4-10-3

a97a62f8 · updated version number · Apr 07, 2017

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release-4-10-2

3161277a · corrected problem with real fftw in 32 bit on avx · Apr 05, 2017

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release-4-10-1

3715d94b · removed indexing bug for intel (sse4) backend. · Apr 04, 2017

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release-4-10-0

b61b32ea · added new arm backend. · Apr 03, 2017

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